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fedl7022-01-06 1 semiconductor this version: may 2000 previous version: sep. 1999 ml7022-01 single rail dual channel pcm codec 1/20 general description the ml7022 is a two-channel single-rail codec cmos ic for voice signals ranging from 300 to 3400hz. this device contains two-channel analog-to-digital (a/d) and digital-to-analog (d/a) converters on a single chip. the ml7022 is designed especially for a single power supply and low power applications and achieves a reduced footprint. the ml7022 is best suited for line card applications with easy interface to subscriber line interface circuits (slics). the slic interface latches are embedded onto this codec, thus eliminating the need for external components and optimizing board space. features ? single 5 v power supply operation ? using ? - adc and dac technique ? low power consumption 2-channel operating mode: typical: 70 mw max.: 90 mw 1-channel operating mode: typical: 40 mw max.: 55 mw power saving mode: (cpd1 = cpd2 = ?0?) typical: 9 mw max.: 12.5 mw power down mode: (pdn = ?0?) typical: 0.05 mw max.: 0.25 mw ? itu-t companding law - -law ? built-in dual 3-bit latches with cmos drive capability ? serial pcm interface ? master clock: 4.096 mhz ? transmission clocks: 256 to 4096 kbps ? adjustable transmit gain ? built-in reference voltage supply ? analog output can directly drive a 600 ? line transformer ? latched content echo-back function ? package type: 30-pin plastic ssop (ssop30-p-56-0.65-k) (product name: ml7022-01mb)
fedl7022-01-06 1 semiconductor ml7022-01 2/20 block diagram rc lpf rc lpf rc lpf rc lpf ? - ad conv bpf bpf lpf lpf ? - ad conv ? - da conv ? - da conv ain1 gsx1 compressor compressor expander expander dout tcont aout1 aout2 rcont bclk xsync rsync din ain2 gsx2 latch c1a c2a c3a c1b c2b c3b power cont. & clock gen. pdn mck sg gen. sgc v dd ag dg
fedl7022-01-06 1 semiconductor ml7022-01 3/20 pin configuration (top view) 30-pin plastic ssop 1 v dd test1 test2 ain1 gsx1 aout1 test3 ag sgc aout2 gsx2 ain2 test4 test5 v dd pdn c1a c2a c3a rsync xsync dg dout din bclk mck c3b c2b c1b test6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
fedl7022-01-06 1 semiconductor ml7022-01 4/20 pin descriptions pin symbol type description 1v dd ? power supply * 2 test1 i device test pin 1 3 test2 i device test pin 2 4 ain1 i channel-1 transmit op-amp input 5 gsx1 o channel-1 transmit op-amp output 6 aout1 o channel-1 receive output 7 test3 i device test pin 3 8 ag ? analog ground 9 sgc o signal ground 10 aout2 o channel-2 receive output 11 gsx2 o channel-2 transmit op-amp output 12 ain2 i channel-2 transmit op-amp input 13 test4 i device test pin 4 14 test5 i device test pin 5 15 v dd ? power supply * 16 test6 i device test pin 6 17 c1b o c1b bit latched output 18 c2b o c2b bit latched output 19 c3b o c3b bit latched output 20 mck i master clock (4.096 mhz) 21 bclk i shift clock for the din and dout 22 din i data input 23 dout o data output 24 dg ? digital ground 25 xsync i transmit synchronizing signal 26 rsync i receive synchronizing signal 27 c3a o c3a bit latched output 28 c2a o c2a bit latched output 29 c1a o c1a bit latched output 30 pdn i power down control * v dd of pin 1 and v dd of pin 15 are connected internally, but these pins must be connected on the printed circuit board.
fedl7022-01-06 1 semiconductor ml7022-01 5/20 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? ?0.3 to +7.0 v analog input voltage v ain ? ?0.3 to v dd +0.3 v digital input voltage v din ? ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to +150 c recommended operating conditions parameter symbol condition min. typ. max. unit power supply voltage v dd voltage must be fixed 4.75 5.0 5.25 v operating temperature t op ? ?40 ? +85 c analog input voltage v ain gain = 1 ? ? 3.4 v pp high level input voltage v ih 2.2 ? v dd v low level input voltage v il all digital input pins 0?0.8v mck frequency f mck mck ?0.01% 4096 +0.01% khz bclk frequency f bclk bclk 256 ? 4096 khz sync pulse frequency f sync xsync, rsync ? 8 ? khz clock duty ratio d clk mck, bclk 40 50 60 % digital input rise time t ir ??50ns digital input fall time t if all digital input pins ??50ns mck to bclk phase difference t mb mck, bclk ? ? 50 ns t xs bclk to xsync 50 ? ? ns transmit sync pulse setting time t sx xsync to bclk 50 ? ? ns t rs bclk to rsync 50 ? ? ns receive sync pulse setting time t sr rsync to bclk 50 ? ? ns sync pulse width t ws xsync, rsync 1 bclk ? 100 s din set-up time t ds din 50 ? ? ns din hold time t dh din 50 ? ? ns r dl pull-up resistor, dout 0.5 ? ? k ? dout ? ? 50 pf digital output load c dl c1a, c2a, c3a,c1b, c2b, c3b ? ? 50 pf bypass capacitor for sgc c sg sg to ag 0.1 ? ? f
fedl7022-01-06 1 semiconductor ml7022-01 6/20 electrical characteristics dc and digital interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit i dd1 2ch operating mode, no signal pdn = ?1?, cpd1 = cpd2 = ?1? ? 14.0 18.0 ma i dd2 1ch operating mode, no signal pdn = ?1?, cpd1 = ?1?, cpd2 = ?0? or pdn = ?1?, cpd1 = ?0?, cpd2 = ?1? ? 8.0 11.0 ma i dd3 power saving mode, pdn = ?1?, cpd1 = cpd2 = ?0? ?1.82.5ma power supply current i dd4 power down mode, pdn = ?0? ? 0.01 0.05 ma high level input leakage current i ih all digital input pins v i = v dd ??2.0 a low level input leakage current i il all digital input pins v i = 0 v ??0.5 a dout, pull-up = 0.5 k ? 00.20.4v digital output low voltage v ol c1a, c2a, c3a, c1b, c2b, c3b i ol = 0.4 ma 00.20.4v c1a, c2a, c3a, c1b, c2b, c3b i oh = 0.4 ma 2.5 ? ? v digital output high voltage v oh c1a, c2a, c3a, c1b, c2b, c3b i oh = 50 a v dd ?0.5 ??v digital output leakage current i o dout high impedance state ? ? 10 a input capacitance c in ??5?pf analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit sgc rise time t sgc sg to ag 0.1 f rise time to 90% of max. level ??10ms transmit analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit input resistance r inx ain1, ain2 10 ? ? m ? output load resistance r lgx 20 ? ? k ? output load capacitance c lgx ??30pf output amplitude v ogx gsx1, gsx2 with respect to sg *1 ?1.13 ? 1.13 v offset voltage v osgx gain = 1 ?20 ? 20 mv *1 0.27 dbm (600 ? ) = 3.17 dbm0 ( -law) = 2.26 v pp
fedl7022-01-06 1 semiconductor ml7022-01 7/20 receive analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) parameter symbol condition min. typ. max. unit output load resistance r lao aout1, aout2 (each) with respect to sg 0.6 ? ? k ? output load capacitance c lao aout1, aout2 ? ? 50 pf output amplitude v oao aout1, aout2, r lao = 0.6 k ? with respect to sg ?1.7 ? 1.7 v offset voltage v osao aout1, aout2 with respect to sg ?100 ? 100 mv ac characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) condition parameter symbol freq. (hz) level (dbm0) min. typ. max. unit loss t1 60 25 45 ? loss t2 300 ?0.15 0.15 0.20 loss t3 1020 reference loss t4 3000 ?0.15 0.02 0.20 loss t5 3300 ?0.15 0.1 0.80 transmit frequency response loss t6 3400 0 gsxn to dout (attenuation) 0 0.6 0.80 db loss r1 100 ?0.15 0.04 0.2 loss r2 1020 reference loss r3 3000 ?0.15 0.07 0.2 loss r4 3300 ?0.15 0.2 0.8 receive frequency response loss r5 3400 0 din to aoutn (attenuation) 00.60.8 db sdt1 3 36 43 ? sdt2 0 36 40 ? sdt3 ?30 36 38 ? sdt4 ?40 30 32 ? transmit signal to distortion ratio sdt5 1020 ?45 gsxn to dout *2 25 29 ? db sdr1 3 36 42 ? sdr2 0 36 39 ? sdr3 ?30 36 39 ? sdr4 ?40 30 33 ? receive signal to distortion ratio sdr5 1020 ?45 din to aoutn *2 25 30 ? db gtt1 3 ?0.2 0.02 0.2 gtt2 ?10 reference gtt3 ?40 ?0.2 0.06 0.2 gtt4 ?50 ?0.6 0.4 0.6 transmit gain tracking gtt5 1020 ?55 gsxn to dout ?1.2 0.4 1.2 db gtr1 3 ?0.2 0 0.2 gtr2 ?10 reference gtr3 ?40 ?0.2 ?0.02 0.2 gtr4 ?50 ?0.6 ?0.1 0.6 receive gain tracking gtr5 1020 ?55 din to aoutn ?1.2 ?0.2 1.2 db nidle t ?? ainn = sg *2 ainn to dout ?1416 idle channel noise nidle r ?? din = 0 code *2 din to aoutn ?610 dbrnc0 *2 c-message filter is used
fedl7022-01-06 1 semiconductor ml7022-01 8/20 ac characteristics (continued) (v dd = 4.75 to 5.25 v, ta = ?40 to +85 c) condition parameter symbol freq. (hz) level (dbm0) min. typ. max. unit av t gsxn to dout v dd = 5 v, ta = 25 c 0.535 0.555 0.574 absolute level (initial difference) av r din to aoutn v dd = 5 v, ta = 25 c 0.806 0.835 0.864 vrms av tt ?0.3 ? 0.3 absolute level (deviation of temperature and power) av rt 1020 0 v dd = 4.75 to 5.25 v ta = ?40 to 85 c ?0.3 ? 0.3 db absolute delay t d 1020 0 a to a mode bclk = 2048 khz ? 0.58 0.6 ms t gd t1 500 ? 0.26 0.75 t gd t2 600 ? 0.16 0.35 t gd t3 1000 ? 0.02 0.125 t gd t4 2600 ? 0.05 0.125 transmit group delay t gd t5 2800 0*3 ? 0.07 0.75 ms t gd r1 500 ? 0.00 0.75 t gd r2 600 ? 0.00 0.35 t gd r3 1000 ? 0.00 0.125 t gd r4 2600 ? 0.09 0.125 receive group delay t gd r5 2800 0*3 ? 0.12 0.75 ms cr t trans to receive 75 83 ? cr r receive to trans 75 80 ? cross talk attenuation cr ch 1020 0 channel to channel 75 78 ? db discrimination dis 4.6 to 72k 0 0 to 4 khz 30 32 ? db out of band spurious obs 300 to 3.4k 0 4.6 khz to 1000 khz ? ?37.5 ?35 db sfd t ? ?50 ?40 signal frequency distortion sfd r 1020 0 0 to 4 khz ? ?48 ?40 dbm0 imd t ? ?50 ?40 intermoduration distortion imd r fa = 470 fb = 320 ?4 2 fa - fb ? ?54 ?40 dbm0 psr t1 0 to 4k 40 44 ? psr t2 4 to 50k 50 55 ? psr r1 0 to 4k 40 45 ? power supply noise rejection ratio psr r2 4 to 50k 100 mvrms *4 50 56 ? db t sd 20 ? 100 t xd1 20 ? 100 t xd2 dout pull-up resister = 0.5 k ? c l = 50 pf and 1 lsttl 20 ? 100 ns digital output delay time t pdc c1a, c2a, c3a, c1b, c2b, c3b c l = 50 pf and 1 lsttl 20 ? 1000 ns dout operation delay time t ddo time of operation start after power on ? 4 ? ms aout signal output delay time t dao time of base band signal output start after power on ?4?ms *3 minimum value of the group delay distortion *4 the measurement under idle channel noise
fedl7022-01-06 1 semiconductor ml7022-01 9/20 timing diagram figure 1 transmit side timing diagram figure 2 receive side timing diagram figure 3 transmit side bit configuration figure 4 receive side bit configuration mck t xs d2 1 2345678 t sx t xd1 t sd d3 d4 d5 d6 d7 d8 msd t ws t xd2 t mb bclk xsync dout t rs d2 1 2345678 t sr t ds t ws t dh d3 d4 d5 msd d6 d7 d8 t mb mck bclk rsync din msd ec3a d2 d3 d4 d5 d6 d7 d8 epd1 ec2a ec1a msd ec3b d2 d3 d4 d5 d6 d7 d8 epd2 ec2b ec1b msd d2 d3 1 9 17 25 1 ch1 pcm data echo bits ch2 pcm data echo bits bclk xsync dout msd c3a d2 d3 d4 d5 d6 d7 d8 cpd1 c2a c1a msd c3b d2 d3 d4 d5 d6 d7 d8 cpd2 c2b c1b msd d2 d3 1 9 17 25 1 ch1 pcm data ch1 power down control bit ch2 pcm data latch data ch2 power down control bi t latch data bclk rsync din
fedl7022-01-06 1 semiconductor ml7022-01 10/20 msd d2 d3 d4 d5 d6 d7 d8 cpd1 c3a c2a c1a msd d2 d3 d4 d5 d6 d7 d8 cpd2 c3b c2b c1b msd d2 d3 d4 d5 d6 d7 d8 cpd1 c3a c2a c1a msd d2 d3 d4 d5 d6 d7 d8 cpd2 c3b c2b c1b ch1 pcm input data control data ch2 pcm input data control data ch1 pcm input data control data ch2 pcm input data control data 1 9 17 25 1 9 17 25 msd d2 d3 d4 d5 d6 d7 d8 epd1 ec3a ec2a ec1a msd d2 d3 d4 d5 d6 d7 d8 epd2 ec3b ec2b ec1b msd d2 d3 d4 d5 d6 d7 d8 epd1 ec3a ec2a ec1a msd d2 d3 d4 d5 d6 d7 d8 epd2 ec3b ec2b ec1b ch1 pcm output data echo bit ch2 pcm output data echo bit ch2 pcm output data echo bit ch1 pcm output data echo bit t pdc t pdc bclk xsync rsync din dout c3a, c2a, c1a, c3b, c2b, c1b figure 5 control bit timing and echo back timing
fedl7022-01-06 1 semiconductor ml7022-01 11/20 figure 6 sgc, dout and aout output timing pdn cpd1 (cpd2) dout sgc t sgc t ddo t dao a outn sg level high impedance
fedl7022-01-06 1 semiconductor ml7022-01 12/20 functional description pin functional description ain1, ain2, gsx1, gsx2 ain1 and ain2 are the transmit analog inputs for channels 1 and 2. gsx1 and gsx2 are the transmit level adjustments for channels 1 and 2. ain1 and ain2 are inverting inputs for the op-amp; gsx1 and gsx2 are connected to the output of the op-amp and are used to adjust the level, as shown below. if ain1 and ain2 are not used, connect ain1 to gsx1 and ain2 to gsx2. during power saving and power down mode, the gsx1 and gsx2 outputs are at ag voltage. in the case of the analog input 2.26 vpp at gsx pin with digital output +3.17 dbm0 ( -law). aout1, aout2 aout1 is the receive analog output for channel 1 and aout2 is used for channel 2. the output signal has an amplitude of 3.4vpp above and below the signal ground voltage (sg).when the digital signal of +3.17 dbm0 is input to din, it can drive a load of 600 ? or more. during power saving or power down mode, these outputs are at a high impedance. v dd power supply for +5 v. connect a bypass capacitor of 0.1 f with excellent high frequency characteristics between this pin and the ag pin. although v dd pin 1 and v dd pin 15 are connected internally, these pins must be connected on the printed circuit board. ch1 gain gain = r2/r1 10 r1: variable r2 > 20 k ? c1 > 1/ (2 3.14 30 r1) ch2 gain gain = r4/r3 10 r3: variable r4 > 20 k ? c2 > 1/ (2 3.14 30 r3) ch1 analog input gsx1 ain1 sg r2 r1 c1 ch2 analog input gsx2 ain2 sg r4 r3 c2
fedl7022-01-06 1 semiconductor ml7022-01 13/20 ag ground for the analog signal circuits. dg ground for the digital signal circuits. this ground is separate from the analog signal ground. the dg pin must be connected to the ag pin on the printed circuit board to make a common analog ground. sgc used to generate the signal ground voltage level, by connecting a bypass capacitor. connect a 0.1 f capacitor with excellent high frequency characteristics between the ag pin and the sgc pin. during power down mode, this outputs are at the voltage level of ag with about 50 k ? impedance. mck master clock input. the frequency must be 4.096 mhz. bclk shift clock signal input for the din and dout signals. the frequency, equal to the data rate, is 256 k to 4096 khz. this signal must be synchronized in phase with the mck (generated from the same clock source as mck). figure 1 shows the phase difference of mck and bclk. rsync receive synchronizing signal input. signals in the receive section are synchronized by this synchronizing signal. this signal must be synchronized in phase with the mck (generated from the same clock source as mck). xsync transmit synchronizing signal input. the pcm output signal from the dout pin is output in synchronization with this transmit synchronizing signal. this synchronizing signal synchronizes all timing signals of all section. this signal must be synchronized in phase with the mck (generated from the same clock source as mck).
fedl7022-01-06 1 semiconductor ml7022-01 14/20 din din is a data input pin. the voice band signal is converted to an analog signal in synchronization with the rsync signal and bclk. the analog signal of channel 1 is output from aout1 pin and the analog signal of channel 2 is output from aout2 pin. the 28 bit signal structure is shown in figure 4. it consists of voice band pcm signals (8 bits each), the general- purpose latch signal (6 bits total), the power down control signal (1 bit per channel) and empty bits (4 bits). the signal is shifted at a falling edge of the bclk signal and latched into the internal register when shifted by 28 bits. the start of the pcm data (channel 1?s msd) is identified at the rising edge of rsync. the general purpose latch signal (c3a, c2a, c1a, c3b, c2b, c1b) are output from six latch output pins. when the cpd1 (bit of din) = ?0?, channel 1 block is in a power down state. when the cpd2 (bit of din) = ?0?, channel 2 block is in a power down state. dout dout is a data output pin. the signal consist of a total of 28 bits containing the voice band pcm signals (each channel 8 bits), the echo bit (6 bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). the output cording format follows itu-t recommendation on coding law. the output signal is output from channel 1?s msd bit in a sequential order, synchronizing with the rising edge of the bclk signal. the first bit of dout may be output at the rising edge of the xsync signal, based on the timing between bclk and xsync. this pin is in a high impedance state during power down state. a pull-up resistor must be connected to this pin because it is an open drain output. table 1 the output cording format pcmin/pcmout -law input/output level msdd2d3d4d5d6d7d8 + full scale 10000000 +0 11111111 ?0 01111111 ? full scale 00000000
fedl7022-01-06 1 semiconductor ml7022-01 15/20 c1a, c2a, c3a, c1b, c2b, c3b general-purpose latched output signal. c1a, c2a, c3a, c1b, c2b, c3b bits of din are latched using internal timing. these outputs can drive a lsttl/cmos device without external resistor. pdn power down control signal. when pdn is at logic ?0? level, both channel 1 and channel 2 circuits are in the power down state. also, all internal latches are in initial state (logic ?0? level). test1, test2, test3, test4, test5, test6 these pins are used for device test. these device test pin must be connected to the ag pin.
fedl7022-01-06 1 semiconductor ml7022-01 16/20 table 2 condition of dout by the power control pdn cpd1 cpd2 ch1 pcm data ch2 pcm data ch1 echo bit ch2 echo bit 00/10/1hhhh 1 0 0 11111111 11111111 1 1 0 operate 11111111 1 0 1 11111111 operate 1 1 1 operate operate latched data latched data table 3 condition of the latched output by the power control pdn cpd1 cpd2 lin c1a, c2a, c3a c1b, c2b, c3b 00/10/1 l l 10/10/1 0 latched data latched data 0/1 0/1 0/1 1 l l table 4 condition of the analog output by the power control pdn cpd1 cpd2 gsx1 gsx2 aout1 aout2 sgc 00/10/1 high impedance high impedance high impedance high impedance *5 100 high impedance high impedance high impedance high impedance operate 1 1 0 operate high impedance operate high impedance operate 101 high impedance operate high impedance operate operate 1 1 1 operate operate operate operate operate *5 the voltage level of ag with about 50 k ?
fedl7022-01-06 1 semiconductor ml7022-01 17/20 application circuits ml7022 a in1 gsx1 a out1 a in2 gsx2 a out2 sgc a g dg v dd dout din mck bclk xsync rsync pdn test1 test2 test3 test4 test5 test6 c1a c2a c3a c1b c2b c3b 2ch multiplex pcm signal output 2ch multiplex pcm signal input master clock & bit clock input master clock & bit clock input power down control 0: power down/1: operation latch output channel 1 analog input channel 1 analog output channel 2 analog input channel 2 analog output 0 v +5 v 1 k ? +5 v 0.1 f 0.1 f 1 f +
fedl7022-01-06 1 semiconductor ml7022-01 18/20 recommendations for actual design ? to assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and dg pin each other as closely as possible. connect to the system ground with low impedance. ? unless unavoidable, use short lead type socket. ? when mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than ?0.3 v even instantaneously to avoid latch-up phenomenon when turning the power on. ? use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device.
fedl7022-01-06 1 semiconductor ml7022-01 19/20 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop30-p-56-0.65-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.19 typ. 5 rev. no./last revised 5/dec. 5, 1996 (unit: mm)
fedl7022-01-06 1 semiconductor ml7022-01 20/20 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2000 oki electric industry co., ltd.

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